Electronic musical instrument

ABSTRACT

An electronic musical instrument comprising detection means to detect time positions of an initial part and a terminal part of a voice, extraction means to extract pitch data of the voice, a plurality of processing means to subject the pitch data to different processing operations, means to successively select the processed pitch data of the plurality of processing means in correspondence with the respective detected time positions, and musical sound production means to produce a musical sound on the basis of the processed pitch data delivered from the selection means.

This application is a continuation of application Ser. No. 291,435,field Dec. 28, 1988, and now abandoned which is a Reissue of Ser. No.06/583,091 filed Feb. 23, 1984 and issued as U.S. Pat. No. 4,633,748 onJan. 6, 1987.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an electronic musical instrument whichgenerates waveforms electronically, and more particularly to anelectronic musical instrument which produces musical soundsautomatically without the operations of keys etc.

2. Description of the Prior Art

The progress of electronics has made it possible to electronicallygenerate a musical sound waveform and to produce a musical sound with aloudspeaker. Apparatuses exploitating this technology are usually termed"electronic musical instruments". In general, the electronic musicalinstruments employ a method in which a musical sound to be produced isselected by a key. Further, they can produce the tone of a piano or anyother musical instrument by assigning it with a lever switch or thelike.

Since the electronic musical instrument selects musical sounds with keysas described above, the performance requires the technique of a pianoand experience in the operations of the keys thereof. In other words,playing a person's accompaniment, for example, cannot be easily done andis possible for only those skilled in operating the electronic musicalinstrument. This signifies the problem that the conventional electronicmusical instrument which is operated with keys cannot be simply playedby anybody.

On the other hand, there are also apparatuses which convert a voice andproduce the converted sound without using keys, for example, a musicalsound signal conversion apparatus (Japanese Patent ApplicationPublication No. 52-40973) which multiplies or demultiplies thefundamental frequency of a voice signal to produce a sound. In theJapanese Patent Application Publication, the fundamental frequency isobtained by detecting a zero-cross point of an input voice signal in ananalogue manner. Thus, it is difficult to detect and process the inputvoice signal to produce the good musical sound.

SUMMARY OF THE INVENTION

An object of the present invention resides in providing an electronicmusical instrument which can be simply played alone or for accompanimentwithout any special operating skill and which detects and processes aninput voice signal in a digital manner, thereby producing a bettermusical sound.

According to one feature of the present invention, there is provided anelectronic musical instrument comprising conversion means for convertinga voice to digital data, extraction means for extracting a pitch of saiddigital data obtained by the conversion means, process means forprocessing the output of said extraction means, and musical toneproduction means for receiving the output of said process means andproducing a musical tone in accordance with said output of the processmeans.

According to another feature of the present invention, there is providedan electronic musical instrument comprising detection means fordetecting a time position of at least an initial part of voice and aterminal part of voice, extraction means for extracting pitch data ofvoice, plural process means for processing said pitch data in adifferent manner, selection means for successively selecting processedpitch data of said plural process means in correspondence with saiddetected time position and musical tone production means for producing amusical tone on a basis of the processed pitch data deprived from saidselection means.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of a total system of an embodiment of thepresent invention;

FIG. 2 is more detailed block diagram of an embodiment of the invention;

FIG. 3A depicts a wave form diagram of the input voice and FIG. 3Brepresents three value data in accordance with the input voice;

FIG. 4 is a detailed circuit diagram of three-valuing portion of FIG. 2;

FIG. 5 shows a general timing chart of the embodiment of the presentinvention;

FIG. 6 shows a detailed timing chart of the embodiment of the presentinvention;

FIG. 7 shows a circuit diagram of the shift register and selector ofFIG. 2;

FIG. 8 is a block diagram of an embodiment of the present invention, inwhich the adder/subtracter circuit 30 and memory 31 is commonly used;

FIG. 9 shows a circuit diagram of the multiplication circuit 28, windowprocess circuit 29, adder/subtracter circuit 30, memory 31 and maximumvalue detector 32 of FIG. 2;

FIG. 10 represents a detailed circuit diagram of an embodiment of theerror elimination unit 7 of FIG. 1;

FIG. 11 is a timing chart of the embodiment of FIG. 10;

FIG. 12 is a diagram showing one example of the inputs of the pitch dataand outputs of the latch circuit of the embodiment of FIG. 10;

FIG. 13 shows a diagram of another example of the inputs of the pitchdata and outputs of the latch circuit of the embodiment of FIG. 10;

FIG. 14 shows a detailed block diagram of the running averagecalculation portion 8 of FIG. 1;

FIG. 15 is a timing chart of the running average unit of FIG. 14;

FIG. 16 represents a detailed block diagram of the pitch data controlportion 10 of FIG. 1;

FIG. 17 shows a timing chart of the relationship of the respective flagsand pitch data items in FIG. 16; and

FIG. 18 shows a relationship between the count values of the countersand pitch data in FIG. 16.

PREFERRED EMBODIMENTS OF THE INVENTION

Unlike the prior art wherein the musical scale and timing of a musicalsound are selected with a key, in the present invention a person givesthe musical scale and timing of a musical sound with his or her voice.

FIG. 1 shows a block diagram of an embodiment of the present inventionand a construction of an electronic musical instrument in which amusical sound is produced in accordance with a voice input. The outputof a microphone 1 in which the voice is converted to an electric signalis applied to a preprocessing unit 2. The output of the preprocessingunit 2 is connected to a pitch extracting unit 3. The output of thepitch extracting unit 3 .Iadd.for the determination of pitch in themusical sound .Iaddend.is supplied to a processor (CPU) 5 through alatch 4. The output of the processor 5 is connected to the pitchextracting unit 3, memory unit 6, error removing unit 7, running averagearithmetic unit 8, and flag formation unit 9. The output of the memoryunit is applied to the error elimination unit 7 and pitch data controlunit 10, and the output of the error elimination unit 7 is supplied tothe running average arithmetic unit 8 and pitch data control unit,respectively. The output of the running average arithmetic unit 8 issupplied to the pitch data control circuit 10. The output of the pitchdata control unit 10 is applied to a code generator 11. The output ofthe code generator 11 is connected to a musical tone generator 12, theoutput of which is connected to a speaker in which the electric signalis converted to a sound.

The voice signal converted into the electric signal is applied to thepreprocessing unit 2, thereby causing it to be preprocessed. Thepreprocessing is firstly conducted by removing a signal outside adesired band by a low pass filter (LPF), and so on. The removal of thesignal outside the band is performed to prevent an error of the pitchextraction which is done in the next stage. Further, the preprocessingis conducted to amplify the input voice signal, the outside portion ofthe band of which is removed to have a predetermined amplitude by usingan automatic gain control circuit.

The aforementioned input voice signal of the predetermined amplitude isconverted to digital data by an analog/digital converter. Theaforementioned amplification for producing a predetermined amplitude isperformed to cause the bit number of the output of the analog/digitalconverter to be effective.

The voice signal dealt with the preprocessing unit 2, namely, digitalvoice signal, is applied to the pitch extraction unit 3. The pitchextraction unit 3 extracts a pitch of a basic frequency of the inputvoice signal by the processor (CPU) 5. The pitch extracting unit 3comprises a voice data quantization circuit, a scale extracting circuit,and a three value correlation process circuit, thereby enabling anextraction of the pitch of the input voice. The data quantizer circuitsuccessively obtains the maximum value and minimum value of the digitalvoice data over a specified period of time, and determines respectivethreshold levels for, e.g., three-valuing by the use of these maximumand minimum values. It three-values the input signal with the thresholdlevels. The musical scale extractor circuit is a circuit by which thethree-valued voice data obtained by the three-valuing operation with thedigital voice data is delayed in correspondence with a musical scale tobe extracted, whereupon the delayed data and the input data aremultiplied. A correlation concerning times is then made by this circuit.The resultant data represents the mere correlation of times between thedelayed data and the input data, and it is further processed to extractthe pitch. The extraction is executed by the aforementioned three-valuecorrelation processing circuit. The three-value correlation processingcircuit is a circuit which carried out window processing for the pitchextraction. More specifically, since the plurality of data are providedfrom the musical scale extractor circuit in correspondence with themusical scale to be extracted, they are subjected to the windowprocessing by the three-value correlation processing circuit, that is,they are weighted in relation to the musical scale and are cumulated forthe specified period of time (1 frame). A maximum value is obtained fromamong the cumulative values (cumulative values corresponding to delaytimes), and the pitch is found on the basis of the delay timecorresponding to the maximum value and delivered as an output. Thisoutput is data relevant to the pitch of the fundamental wave of thevoice (including harmonic waves) received as the input.

The pitch data delivered from the pitch extraction unit 3 is stored inthe memory unit 6 through the latch 4 as well as the processor 5. Theerror elimination unit 7 is a circuit which detects the specified changeof pitch data, for example, the change of at least 1 octave particularlyin 1 frame by the use of the data stored in the memory unit 6 and whichrestores the data to the status before the change upon detecting thecharge. In addition, there can also be a sudden change of the musicalscale. In this event, the data changes after 1 frame. The data havinghad the error eliminated in the error elimination unit 7 is averaged inthe running average calculation unit 8. The average is, for example, anarithmetical mean obtained by weighting the average up to the presenttime and data over 6 frames. More specifically, the averaging operationin the calculation unit 8 is such that the pitch data in frame unitsuccessively received are stored in a shift register and shifted inframe unit, that the shift data of the 6 stages of the shift registerand the average value are selected for cumulation within 1 frame periodby a selector, and that less significant bits are rounded off by way ofexample.

The averaged data is delivered from the running average calculation unit8 and is applied to the pitch data control unit 10, in which it isprocessed for producing a musical sound. In other words, the errorelimination unit 7 mentioned above detects and obviates the malfunctionof the pitch extraction attributed to external noise etc., to eliminatethe step-like great change of data resulting from the malfunction of thepitch extraction. Also, the running average calculation unit 8hysteretically averages the subtle change of data of the erroneous pitchextraction attributed to the subtle pitch change of the input voice orthe like, to stabilize the data.

The human voice, which is not limited to singing, has consonant andvowel sounds. Although the pitches of dundamental waves are contained inmany vowels, these are very few in some consonants. For this reason,while only a consonant is being produced (for example while "S" is beingproduced in case of giving forth "SA"), the pitch of the fundamentalwave is sometimes extracted erroneously. It is the pitch data controlunit 10 that prevents the malfunction of the musical sound productionascribable to such erroneous extraction, so as to establish the musicalscale of the received voice. Using the power of the voice or the dataof, e.g., the voice input detection, this control unit selects for itsoutput the data stored in the memory unit 6, the output data of theerror elimination unit 7 or the output data of the running averagecalculation unit 8.

The code generator 11 is a circuit which converts the output of thepitch control unit 10 into the code of the musical sound to be producedin the musical sound producer 2, namely, musical sound data.

The pitch extraction unit 3, memory unit 6, error eliminating circuitand running average calculating unit 8 are controlled by the processor5. The pitch data control unit 10 and code generator unit 11 arecontrolled by the processor 5 through the flag formation unit 9. Inother words, the flag is set in the flag formation unit 9 by theprocessor 5, thereby causing the pitch data control unit 10 and codegenerator 11 to be operated by the flag.

The output of the code generator 11, namely, the covered data, isapplied to the musical tone generating unit 12, thereby designating themusical tone which should be produced from the speaker 13. In otherwords, the musical tone electric signal (analog signal) designated bythe converted data of the code generator 11 is produced at the musicaltone generator unit 12, thereby to be applied to the speaker 13. As aresult, the musical tone is produced by the speaker 13 in accordancewith the input voice applied to the microphone 1.

FIG. 2 shows a more detailed block diagram of a second embodiment of theinvention. Particularly, it shows a detailed block diagram of thepreprocessing unit 2 and pitch extraction unit 3 shown in FIG. 1. Thevoice signal, namely, the electric signal converted from the voiceinputted from the microphone 1, is inputted into an automatic gaincontrol circuit 15 through a low pass filter 14 and the output thereofis applied to an analog/digital converter 16. The output of theanalog/digital converter is applied to a maximum value calculationportion 18, a minimum value calculation portion 19, and the first inputof a comparation 20 of the three value quantization unit 21, and thepower computation unit. The three value quantization unit 21 comprisesthe maximum value calculating unit 18, the minimum value calculatingunit 19, a comparator 20, multiplication circuits 22 and 23, and amemory 25. The output of the power computation unit 17 is connected to apower extraction terminal 24. The outputs of the maximum calculatingunit 18 and the minimum value calculating unit 19 are respectivelyapplied to the first inputs of the multiplication circuits 22 and 23. Acoefficient data ε ₁, ε₂ are supplied to the multiplication circuits 22and 23. The outputs of the multiplication circuits 22 and 23 areinputted to the second and third inputs of the comparator 20. The outputof the comparator 20 is applied to a shift register 26 as the output ofthe three value quantization unit 21. A plurality of the first outputsof the shift register 26 are correspondingly supplied to a plurality ofinputs of a selector 27. The output of the last stage of the shiftregister 26 and the output of the selector 27 are applied to the firstand second inputs, respectively. The output of the multiplicationcircuit 28 is inputted to the first input of the adder/subtracter 30through a window processing circuit 29. The output of theadder/subtracter 30 is connected to a memory 31. The output of thememory 31 is applied to the second input of the adder/subtracter 30 andthe input of a maximum value detector 32. Control outputs of a controlunit 33 are respectively applied to control inputs of a three valuequantization unit 21, selector 27 and window processing circuit 29. Anoutput of the maximum value detector unit 32 is applied to a scale codeterminal 34.

By way of example, a musical sound produced from a musical instrument ofthe voice of a man is converted into an electric signal by themicrophone 1. The voice signal or electric signal is applied to thelow-pass filter 14 and has a higher frequency region thereof removed.The low-pass filter 14 is a low-pass filter having a cutoff frequencyof, e.g., 900 Hz which serves to remove noise outside the voicefrequency band and also to control the band of the voice signal. Thisfilter may well be a band-pass filter. The malfunctions of pitchextraction to be executed below, attributed to higher harmonics etc.,are prevented by the filter 14. The band-limited voice signal having hadthe noise outside the band eliminated is amplified in the automatic gaincontrol circuit 15 so as to become a specified amplitude value. Thecircuit 15 is inserted in order to validate the output bits of theanalog-to-digital converter circuit 16 of the succeeding stage. By wayof example, let it be supposed that the maximum and minimum conversionvoltages of the A/D converter circuit 16 be ±5 V. Then, when theabsolute values of the maximum value and minimum value of the output ofthe automatic gain control circuit 15 are greater than 5 V, the outputof the A/D converter circuit 16 becomes invalid. Further, in a casewhere the absolute values of the maximum and minimum value of the outputof the automatic gain control circuit 15 are much smaller than 5 V andare, e.g., 0.5 V, the digital data value of the A/D converter circuit 16also becomes small, and the more significant bits thereof become lowlevel, so that the number of valid bits decreases. To the end ofpreventing these drawbacks, the automatic gain control circuit 15operates so that the maximum and minimum values of the output thereofmay not exceed the conversion voltage range of the A/D converter circuit16 and may not become small absolute values. However, the automatic gaincontrol circuit 15 does not operate so as to render the maximum andminimum values constant at all times, but it operates so as to have again dependent upon the maximum and minimum values of the voice signaland to deliver a signal of an amplitude value within a substantiallyspecified range. In the absence of the input, the gain become maximal,but the output is naturally null.

The voice signal converted into the specified amplitude value isprovided from the automatic gain control circuit 15, and is convertedinto the digital data value in the analog-to-digital converter circuit16.

The power computation unit 17 is a circuit which takes the absolutevalue of the digital output of the A/D converter circuit 16 andcumulates such absolute values over 1 frame of a specified range. Thatis, the digital outputs of the A/D converter circuit 16 have their signsremoved and are cumulated. The cumulated result is a value relevant tothe power of the voice signal, and the power computation unit 17delivers the result to the power extraction terminal 24.

The output of the analog-to-digital converter circuit 16 is applied tothe maximum value calculating unit 18 and the minimum value calculatingunit 19 of the three value quantization portion 21. The maximum andminimum values during a predetermined period of the converted voicedigital data are detected at the maximum value calculating portion 18and the minimum value calculating portion 19. This is performed forobtaining a threshold level used for converting the analog signal tothree values.

The maximum and minimum values are detected at the maximum valuecalculating portion 18 and the minimum value calculating portion 19. Themaximum and minimum values are multiplied by the predeterminedcoefficient ε₁ and ε₂ at the multiplication circuits 22 and 23, therebystoring them in the memory 25. The comparator 20 compares the digitaldata output of the analog-to-digital converter 16 with the thresholdlevels. As the maximum and minimum values are multiplied by ε₁ =0.4 andε₂ =0.4, for example, in the multiplication circuits 22 and 23, athreshold level is provided in proportion to an amplitude value of theinputted signal. The conversion to three values is performed in thecomparator unit 20 in accordance with a threshold level which isnormalized at the maximum and minimum amplitude value.

FIGS. 3A and 3B show a wave form diagram of the voice data, namely, theinput of the analog-to-digital converter 16 and the signal obtained byconverting said data to three values.

When voice data is larger than a threshold level TH obtained bymultiplying the maximum value by ε₁, a three value data is "1" (as shownin the ranges a₁ to a₅ of FIG. 3B). When voice data is smaller than athreshold level TL obtained by multiplying the minimum value by ε₂, athree-valued data is -1" (as shown in the ranges b₁ and b₂). If voicedata is between the threshold level TH and the threshold level TL, thethree-valued data is "0". The three-valued data comprises two bits,namely, a sign bit and a data bit, as shown in a table 1. When the datais "0" or "1", the sign bit is "0". When the data is "-1", the sign bitis "1". The data bit shows its absolute value. When the three-valueddata is "±1", the data bit is " 1". When the three-valued data is "0",the data bit is "0".

                  TABLE 1                                                         ______________________________________                                        three-                                                                        valued data     sign data                                                                              data bit                                             ______________________________________                                        -1              1        1                                                    0               0        0                                                    1               0        1                                                    ______________________________________                                    

The comparator 20 provides three-valued data with regard to apredetermined period, namely, one frame period, using threshold levelsobtained from the maximum and minimum data during the predeterminedperiod. These sequential operations are controlled by control signalsproduced by the control portion 33.

The output of the comparator 20, namely, the three-valued data, isapplied to the shift register 26 and is sequentially shifted. Shiftedlast data of the shift register is added to the first input data of themultiplication circuit 28. The data following the last shifted data isstill stored in the shift register. A plurality of data which is delayedby the predetermined number of steps, namely, the number of shiftclocks, is selected by the selector 27 in accordance with a selectionsignal produced by the control unit 33, thereby to be applied to thesecond input of the multiplication circuit 28. The data applied to thefirst and second inputs of the multiplication circuit 28 are multipliedtherein. The multiplication is conducted to obtain the productxj·x(j+τi), supposing that the last shifted data is xj and the datadelayed by a predetermined clock τi from the data xj is x(j+τi). Thenecessary number of the multiplication is conducted within one shiftclock and the output thereof is supplied to the first input of theadder/subtracter circuit 30 through the window processing circuit 29.The necessary number of the multiplication is selected by the controlunit 33 and corresponds to a scale. It is conducted 38 times as thetotal amount of delay time τ₀ ˜τhd 37 corresponding to a scale E₂ ˜F₅.Supposing that a shift clock frequency fs is 32.768 KHz, the scalefrequency fi corresponding to the delay time is expressed as fi=fs/τi.τi is in proportion to the twelfth root of 2. τi, corresponding to F₅,E₅, . . . F₂, E₂, is expressed as τ₃₇ =46, τ₃₆ =49 . . . τi=373, and τ₀=395, respectively.

The window processing circuit 29 multiples a coefficient correspondingto a delay selected by the selector 27. Supposing that the coefficient,namely, the window value is w (τi), the value inputted to theadder/subtracter circuit 30 is xj·x(j+τi)·w(τi). The coefficient isselected in accordance with the select signal supplied to the selector27 from the control circuit 33. The adder/subtracter circuit 30 andmemory 31 are used for accumulation. The output of the memory is appliedto the second input of the adder/subtracter in accordance with τi toperform an adding and subtracting operation with regard to the output ofthe window processing circuit 29, resulting in storing the output in thememory 31 again. The data to be stored in the memory 31 is as follows.##EQU1## where N represents the number of a shifting, namely, that of acounting with regard to τi within the predetermined range. w(τi) isconstant as to j in the equation (1). Therefore, the following equationis established. ##EQU2## where R(τi) represents an accumulated value ofxj·x(j+τi) and a correlation value corresponding to a predetermined timedelay.

As apparent from Equation (2), the aforementioned w(τ_(i)) is multipliedby the correlative value corresponding to the specified delay time andbecomes the window value corresponding to the delay time of the windowfunction. Thus, the error of overtone extraction attributed to thethree-valuing operation can be prevented (window processing). In somecases, the second or third higher harmonic component is higher in levelthan the fundamental wave. It is therefore important to execute themultiplication of the window value, namely, the window processing.

The output of the memory portion 31 is applied to the maximum valuedetector portion 32, and the maximum value in the memory portion 31 isdetected. Values stored in the memory portion 31 are cumulative valueseach of which is the result obtained by multiplying the value of thespecified time delay and the present-time value and then subjecting theproduct to the window processing. Therefore, they are valuescorresponding to the respective pitches or frequency components of inputvoice signals within a specified period of time. (The specified periodof time indicates 1 frame. In a case where 1 frame consists of 800system clock intervals, the stored values become cumulative values of400 times.) That is, the value detected in the maximum value detectorportion 32 is the maximum value of the signals of the respectivefrequency components of the input voice signals within the specifiedperiod of time.

The maximum value detector portion 32 turns the pitch or frequency datahaving the maximum value into a code by way of example, to deliver thecode to the musical scale code terminal 34.

According to the above-described operation, the musical scale code dataassociated with a keynote of the voice signal is outputted from themusical scale code terminal 34 and is stored in the latch 4. Then, theoperation of an error elimination, running average, and so on areconducted.

FIG. 4 shows a detailed circuit diagram of the three-valuing portion 21and power computation portion 17 of FIG. 2. The output of theanalog/digital converter 16 is stored in the buffer register 35. Theoutput is applied to a minuend input B of the adder/subtracter and theinputs of the registers 37, 38. The output C of the adder/subtractercircuit 36 is inputted to the latch circuit 39. The data output fromROM40 is applied to the inputs of latch circuits 41 and 42.

The outputs of the latch circuits 37, 39, 41, 42 are commonly connectedthrough the respective gate circuits 43 to 47 and are inputted to asubtrahend input A of the adder/subtracter circuit 36 and an addressinput of ROM40. These gate circuits 43 to 47 are turned to "on" during apredetermined period T₁ to T₅ within one frame. A carry output D of theadder/subtracter circuit 36 is connected to the respective inputs oflatch circuits 48 and 49, the first input of an AND gate 50, and thefirst input of the AND gate 52 through an inverter 51.

The output of the latch circuit 48 is applied to the shift register 26as the sign bit and is supplied to the first input of an OR gate 53. Theoutput of the latch circuit 49 is connected to the second input of theOR gate 53 through an inverter 54. The output of the OR gate 53 isapplied to the shift register 26 as the data bit. The outputs of the ANDgates 50 and 52 are applied to the clock terminals of the latch circuits38 and 37.

The operation of an embodiment of the present invention will bedescribed by referring to timing charts of FIG. 5 and FIG. 6.

In the embodiment of the present invention, data is processed in a frameunit as mentioned above. 1 frame includes 800 data, and the maximumvalue and minimum value of the amplitudes of the data are calculated inframe units. The maximum and minimum values are determined after thelast data of 1 frame has been received as an input. The comparatorportion 20 compares the next input data with threshold levels concernedwith the maximum and minimum values.

More specifically, as illustrated in FIG. 5 by way of example, themaximum and minimum values obtained in a frame (n-1) are employed forthe comparisons of data in the next frame (n). Further, the valuesobtained in the frame (n) are used in a frame (n+1). In other words, thethree-value quantization portion 21 detects the maximum and minimumvalues of the immediately preceding frame, finds the threshold levelsfrom these maximum and minimum values and finally three-values the dataof the next frame in the comparator portion by the use of the levels.

Referring back to FIG. 4, the data received from the analog-to-digitalconverter circuit 16 is stored in the buffer register 35 in a period oftime t₁. First, data x₀ shown in FIG. 6 is stored. The data is appliedto the adder/subtracter circuit 36. This adder/subtracter circuit 36operates as an adder circuit when its addition/subtraction control inputSUB receives a high level, and as a subtracter circuit when a low level.Since the low level is applied to the control input SUB of theadder/subtracter circuit 36 except for a period of time t₅, thesubtracter circuit is established during periods of time t₁ -t₄. In theperiod of time t₁, the gate circuit 43 is "on", and data stored in thelatch circuit 37 is applied to the adder/subtracter circuit 36 andsubjected to subtraction. Herein, in a case where the data stored in thebuffer register 35 is greater than the data stored in the latch circuit37, the carry terminal D of the circuit 36 provides the low level. Sincethe latch circuit 37 stores the maximum value, the data having beenstored in the buffer register 35 is stored in the latch circuit 37 onthis occasion. The low level of the carry terminal D is inverted intothe high level by the inverter 51, and this high level enters the ANDgate 52. Therefore, the AND gate 52 turns "on", and a clock φ₃ (t₁ ·φ₃)in the period of time t₁ enters the clock terminal of the latch circuit37, so that the aforementioned data applied to the input of the circuit37 is latched. Conversely, in a case where the data stored in the bufferregister 35 is smaller than the data stored in the latch circuit 37, thecarry terminal D of the adder/subtracter circuit 36 becomes the highlevel. Since the signal or high level is applied to the AND gate 52through the inverter 51, the AND gate 52 turns "off", and the clock t₁·φ₃ does not enter the latch circuit 37. That is, the data stored in thelatch circuit 37 remains unchanged. This operation is executed in theperiod of time t₁.

Next, in the period of time t₂, the gate circuit 44 turns "on" and thedata stored in the latch circuit 38 is applied to the adder/subtractercircuit 36. Likewise to the above, the subtraction is executed in theadder/subtracter circuit, and the magnitudes of the data are compared.In a case where the data stored in the buffer register 35 is smallerthan the data stored in the latch circuit 38, the carry terminal Dprovides the high level. Since the latch circuit 38 stores the minimumvalue, the data stored in the buffer register 35 is latched in the latchcircuit 38 on this occasion by an operation discussed below. The ANDgate 50 is supplied with the high level of the carry terminal D.Therefore, a clock φ₃ (t₂ ·φ₃) in the period of time t₂ during which theAND gate 50 is "on" enters the clock terminal of the latch circuit 38,so that the aforementioned data applied to the input of the circuit 38is stored.

This operation will be repeated as to the data X₀ ˜X₈₉₈. Upon the frameperiod T₅ (namely, the period corresponding to the last data X₇₉₉), thegate circuit 43 is turned "on" at T₁, and the data of the latch circuit37 is stored in ROM 40. That content of the memory which is designatedby the data is applied to the input of the latch circuit 41 and isstored in the latch circuit 41 at a timing of the clock T₅ ·t₁ ·φ₃.Likewise, at a period of t₂ of the period T₅, the gate circuit 44 isturned to "on", thereby applying the data of the latch 38 to ROM 40.That content of the memory which is designated by the dataiis applied tothe input of the latch circuit 42 and is stored in the latch circuit 42at a timing of a clock T₅ ·t₂ ·φ₃. As the data applied to ROM 40 is amaximum and minimum value, the threshold levels corresponding to themaximum value and minimum value are stored in the latch circuits 41 and42 by storing the result multiplied by a predetermined value, forexample, ε₁ =0.4 and ε₂ =0.4 in the memory, the address of which isdesignated thereby. In accordance with the able operation, the thresholdlevels associated with the maximum value and minimum value within oneframe are stored in the latch circuits 41 and 42.

In the remaining period of the data X₀ ˜X₇₉₉, namely, in the period t₃and t₄, an operation to form three values is conducted in parallel withthe above-mentioned operation of detecting threshold level. Thethreshold levels associated with the maximum and minimum values in theprevious frame are then stored in the latch circuits 41 and 42.

Firstly, the data X₀ is stored in the buffer register 35 as explained inthe above prescription. The gate circuit 45 is turned to "on" during theperiod of t₃.

The data stored in the latch circuit 41 is added to the substrahendinput A of the adder/subtracter circuit 36. The content of the bufferregister, namely, the data X₀, is applied to the minuend input B. It isoutputted from the carry terminal D whether one data is larger than theother, and the carry output is stored in the latch 49 at a timing ofclock φ₃ within the period t₃, namely t₃ ·φ₃. When the data stored inthe latch circuit 49 is at a low level, the data X₀ stored in the bufferregister 35 is larger than the threshold level stored in the latchcircuit 41. When the data stored in the latch circuit 49 is at a highlevel, the data X₀ stored in the buffer register 35 is smaller than thethreshold level stored in the latch circuit 41.

Next, at a period t₄, the gate circuit 46 is turned to "on" as is donein the description, and the data stored in the latch circuit 42 appliedto the subtrahend input A of the adder/subtracter 36. On the other hand,the data X₀ is added to the minuend B as is done at a period of t₃. Theinformation of the data's quantity relationship is outputted from thecarry terminal D and is captured by the latch 48 at a clock φ₃ withinthe period t₄, namely, at a timing of t₄ ·φ₃. When the data stored inthe latch circuit 48 is in a low level, the data X₀ stored in the bufferregister 35 is larger than threshold levels stored in the latch 42(which corresponds to the minimum value). Similarly the relationship isreversed when thedata stored is in a high level.

The data of this latch circuit does not charge until the next clock. Atthe same time subtraction result is received and is converted to threevalue data by an encoder comprising an inverter 54 and OR date 53,thereby being supplied to the shift register 26. When the both datumstored in the latch circuits 48 and 49 are in the low level, the datastored in the buffer register 35, namely, the data X₀ is larger than thethreshold level relative to the maximum value, causing the output of theinverter 54 to be at the high level and to be outputted from the OR gate53 as data bit and the low level of the latch circuit 48 is outputted asa sign bit. When both data are in the high levels, the data stored inthe buffer register 35 is smaller than the threshold level relative tothe minimum value. Thus, the output of the latch circuit 49, namely, thehigh level signal, is delivered from the OR gate 53 as the data bit andthe sign bit becomes a high level. In the all other situations, namely,in cases where a signal is smaller than a threshold level relative tothe maximum data and is larger than a threshold level relative to themaximum data, the high level is stored in the latch circuit 49 and thelow level is stored in the latch circuit 48. At this time, the highlevel of the output of the latch circuit 49 is inverted by the inverter54, thereby applying the low level to the OR gate 53 and also applyingthe low level of the output of the latch circuit 48 to the OR gate 53,with the result that the output of the OR gate 53 becomes low level.Thus, the low level is applied to the shift register 26. The output ofthe latch 48, namely, the low level, is delivered as the sign data. Thethree-valued data of the output is the sign data encoded with two bitsas shown in the table 1. The above described operation of the periods oft₃ and t₄, is similar to the operation of detecting the maximum andminimum values, which is described above. Such operation is performed asto X₁ and further X₂ ˜X₇₉₉, successively. Further, such sequentialoperation is performed by changing the threshold level at every frameunit. This is done by simply accumulating the value of the bufferregister 35, at a period of t₅, which was not described in theabove-mentioned operation. At a period of t₅, the gate circuit 47 isturned "on", thereby adding the content of the latch circuit 39 to theinput A of the adder/subtracter circuit 36. The content of the bufferregister 35 is applied to the input B. On the other hand, the low levelis applied to the adder/subtracter control terminal SUB of theadder/subtracter circuit 36, the adder/subtracter circuit 36 performs anadder operation unlike the periods of t₁, t₂, t₃ and t₄. As a result,the data added to the inputs A and B is outputted from the outputterminal C, thereby being supplied to the input of the latch 39. Theoutputted data is received by the latch 39 at a clock of t₅ ·φ₃. Thelatch circuit 39 is reset during the period of T₅ ·t₅, namely, a periodt₅ within the frame period T₅ corresponding to the last data. Thus, thedata X₀ ˜X₇₉₉ within one frame is accumulated, thereby being deliveredfrom the power extraction terminal 11. τ₀ ˜τ₃₇ shown in FIG. 6 show acorrelation calculation performed concerning one data.

Each datum has 40 slots and the calculation is conducted only for τ₀˜τ₃₇ in the embodiment of this invention. The clocks φ₁, and φ₂ show theclocks necessary for a calculation performed at that time.

The adder/subtracter circuit 36 of FIG. 4 detects a start and a initialterminal part of the voice and selects a pitch extraction data.

In the above-described embodiment, it is explained that the input datais the voice signal and any signal may be processed through aquantization, operation, similar to the above-described process.

Further, three value quantization is performed in the above embodimentand other multi-level quantization may be possible by increasing thenumber of the subtraction or the comparison process in accordance withthe periods t₃ and t₄, and by increasing the number of circuitsassociated with it, for example, a ROM and latch circuit.

The processed result thus obtained, namely, the three-valued data, isapplied to the shift register 26, and the correlation and pitchextraction process it performed.

FIG. 7 shows the shift register 26 and selector 27 of FIG. 2.

The shift register 26 comprises the shift registers 26-0 to 26-399 of400 steps. The three value data of the three value quantization portion8, i.e., the output of the OR gate 53 and latch circuit 48 in FIG. 4 isapplied to the shift register 26-0 to 26-399. A two bit parallelshifting is conducted at the shift registers 26-0 to 26-399. The two bitoutputs of the shift register 26-0 are applied to the first input of anexclusive OR gate 28-1 and the first input of the AND gate,respectively. The predetermined outputs of the shift registers 26-0 to26-399 are respectively applied to the first inputs of AND gates 93-1 to56-1 and 93-2 to 56-2. The selection signals from the control units 33are applied to the second inputs of AND gates 93-1 to 56-1 and 93-2 to56-2. The outputs of the AND gates 93-1 to 56-1 are applied to the ORgate 27-1 and the outputs of the AND gates 93-2 to 56-2 are supplied tothe OR gate 27-2. The outputs of the OR gates 27-1 and 27-2 are,respectively applied to the second inputs of the exclusive logic OR gate28-1 and AND gate 28-2 of the multiplication circuit 28. The outputthereof is applied to the window processing circuit 29.

The three valued data of two bits supplied from the three valuequantization portion 21 is supplied to the shift register 26-399 and issequentially shifted in the shift registers 26-399 to 26-0. When thethree-valued data within one frame is stored in the shift registers26-399 to 26-0, the selection signal is delivered from the control unit33. When the AND gates 56-1 and 56-2 are selected, signal linesconnected to the second inputs of the AND gates 56-1 and 56-2 becomehigh level and two bit outputs of the shift register 26-395 aredelivered from the AND gates 56-1 and 56-2. As the second inputs of theother AND gates 57-1 to 93-1 and 57-2 to 93-2 receive low level signalsfrom the control unit 33, the outputs thereof become low levels. Theoutputs of the AND gates 56-1 to 93-1 are applied to the OR gates 27-1and the outputs of the AND gates 56-2 to 93-2 are applied to OR gate27-2. The outputs of OR gates 27-11 and 27-2 produce the same data asthe outputs of the AND gates 56-1 and 56-2, namely, the output of theshift register 26-395. The AND gates 56-1 to 93-1, 56-2 to 93-2 and theOR gates 27-1 and 27-2 operate as a selector for selecting the output ofthe shift register 26 as described above.

As stated before, the first input of each of the AND gates 56-1 to 93-1and 56-2 to 93-2 is supplied with the corresponding one of the specifiedoutputs of the shift register steps 26-0 to 26-399. The specifiedoutputs are the outputs of the register steps which have delaysproportional to the periods of the respective musical scales E₂ -F₅. Forexample, the output of the shift register step 26-395 corresponds to themusical scale E₂, that of 26-373 to F₂, that of 26-36 to E₅, and that of26-35 to F₅. They are successively selected within 1 shift clock, andmultiplications to be described below are executed. The exclusive logicOR gate 28-1 is supplied with the sign bit of the output of the shiftregister step 26-0 and the sign bit of the output of the shift registerstep selected by the selector 27-1. The exclusive logic OR gate is suchthat, when both the first and second inputs are "1" or "0", the outputbecomes "0", whereas when one of the first and second inputs is "1" andthe other is "0", the output becomes "1". Here, the logics "0" and "1"correspond to the foregoing low level and high level respectively.Meanwhile, regarding the signs of the multiplication, when both themultiplier and the multiplicand are minus or plus, the product becomesplus, and when one of them is plus and the other is minus, the productbecomes minus. Therefore, the operations of the exclusive logic OR gate28-1 correspond exactly to the multiplication.

The AND gate 28-2 is supplied with the data bit of the output of theshift register step 26-0 and the data bit of the output of the shiftregister step selected by the selector 27-2. The data bit is 1 bitexcept a sign bit. When both the inputs are "1", the output becomes "1",whereas the output becomes "0" in any other case. These operations areeffected by the AND gate 28-2.

As a result, the multiplication circuit 28 operates as a multiplier unitof 2 bits including a sign as indicated in Table 2. The output of themultiplication circuit 28 is applied to the window processing circuit29, and is multiplied by a coefficient corresponding to the selecteddelay time.

                  TABLE 2                                                         ______________________________________                                                 -1            0       1                                              -1        1            0       -1                                             0         0            0       0                                              1        -1            0       1                                              Three-valued data                                                             ______________________________________                                    

Since the multiplication stated above is executed with the data delayedby the specified time, out output of the multiplication circuit 28becomes data having a correlative value. The specified time delay isdetermined by the shift clock and the number of clock pulses. By way ofexample, assuming the shift clock frequency to be 32.768 kHz, the dalayof the shift register step 26-395 becomes approximately 12 msec, whichcorresponds to approximately 83 Hz in terms of frequency. That is, thecorrelative value becomes a value relevant to 83 Hz (musical scale E₂).This value corresponds to the case of selecting the shift register step26-395, and by selecting the other shift register steps, the correlativevalues of the musical scales corresponding thereto can be obtained.

In the embodiment of FIG. 7, the shift register steps corresponding tothe musical scale extracted within one clock are sequentially selectedand the multiplication is conducted.

Instead of performing the selection corresponding to the aforementionedmusical scale, the outputs corresponding to all of the musical scaletones are respectively added to the multiplier circuits having thenumber of the extraction musical scale tone, and the result is appliedto the up and down counter, thereby using the adder and subtractercircuit 30 and the memory 31 shown in FIG. 2 in common.

FIG. 8 shows the circuit thereof. The sign bit of last shift output ofthe shift register 26, namely, the output of the shift register 26-0 iscommonly connected to the first inputs of the exclusive OR gates 94 to131. The data bit output is commonly connected to the first inputs ofthe AND gates 132 to 169. The sign bit outputs of the shift registers26-395 to 26-46 are selectively applied to the second inputs of theexclusive logic OR gates 94 to 131 and the data bit outputs of the shiftregisters 26-395 to 26-46 are similarly added to the second inputs ofthe AND gates 132 to 169.

In the embodiment of FIG. 6, the data selectively selected within oneshift clock is sequentially multiplied by the last shift output in themultiplier 28, and, in the embodiment shown in FIG. 7, they aremultiplied in separate multiplier circuits. The outputs of themultiplication result are delivered in parallel from the AND gates 132to 169 and the exclusive OR gates 94 to 131 in accordance with therespective time delays. The outputs are applied to clock input terminalsC and the up and down selection terminals S of the up and down counters170 to 207. The outputs of the counters are applied to a maximum valuedetection portion 32'.

In the embodiment of FIG. 7, all the outputs of the shift register steps26-1 to 26-399 corresponding to the musical scales are applied to themultiplication circuit 28 and are respectively multiplied by the outputof the shift register step 26-0. The outputs of the multiplications areapplied to the up/down counters corresponding to the delay times. Theoutputs of the exclusive logic OR gates 94-131 enter the up/downselection terminals S of the respective up/down counters 170-207.Therefore, assuming by way of example that the up/down counters countdown when "1" is applied to the up/down selection terminals S and upwhen "0" is applied, they count up for the multiplied results of +1 anddown for the multiplied results of -1. In addition, when the outputs are"0", they are not counted because no clock data is received. That is,the up/down counters 170-207 have their contents changed incorrespondence with the shift clock intervals. When the operations ofthe up/down counters have been executed for a specified range, forexample, for 1 frame, the outputs thereof become cumulative values. Inother words, the up/down counters correspond to the adder/subtractercircuit 30 and the memory portion 31 in the embodiment of the presentinvention illustrated in FIGS. 2 and 7. The outputs of the up/downcounters 170-207 enter the maximum value detector portion 32'. Unlikethe foregoing maximum value detector portion 19 of the embodiment inFIG. 7, this detector portion 32' includes the function of the windowprocessing circuit 29. Therefore, it multiplies the outputs of theup/down counters 170-207 by the coefficient relevant to the delay timesor by window values and detects the maximum value of the results.Although, the embodiments of the present invention in FIG. 7 and FIG. 8have employed the shift register 26 which shifts and stores thethree-valued data outputs from the comparator portion 20 so as todeliver the data x_(j) and x(j+τ_(i)) delayed by τ_(i) frompredetermined bits, the shift register can be replaced with, forexample, a RAM (random access memory). More specifically, thethree-valued data items provided from the comparator portion 20 aresuccessively written into the RAM in the number of 400 for 1 frame, andin reading out the data x_(j) and x(j+τ_(i)), addresses A_(j) andA(j+τ_(i)) in which they are stored are assigned, whereby the sameoutput data as in the case of employing the shift register can beobtained. Essentially, the shift register etc. are not restrictive, butany circuit arrangement capable of providing the data x_(j) andx(j+τ_(i)) may be adopted.

FIG. 9 shows a circuit diagram of the multiplication circuit 28, windowprocessing circuit 29, adder/subtracter circuit 30, memory portion 31,and maximum value detector 32. The output data of the shift register 26and selector 27 is applied to the multiplication circuit 28. Themultiplication circuit 15 is the same as shown in FIG. 7 and comprisesthe exclusive logic OR gate 28-1 and AND gate 28-2. The sign bit of saidoutput data is applied to the exclusive logic OR gate 28-1 and the databit is applied to the AND gate 28-2.

The output of the exclusive logic OR gate 28-1 is applied to theadder/subtracter control terminal of the adder/subtracter 218 throughthe latch circuit 208 and OR gate 209. The output of the AND gate 28-2is supplied to the control terminal of a group of gate circuit 211through the latch circuit 210. The signal for designating the windowvalue of the control unit 217 is supplied to a read only memory ROM 212and the output thereof is supplied to the first input of the selector213 through a group of gate circuits. The output of the selector 213 isapplied to the first input A of the adder/subtracter circuit 218. Theoutput C of the adder/subtracter circuit 218 is supplied to the latchcircuit 215 and 216 and a randam access memory (RAM). The output of thelatch circuit 215 is added to the second input of the selector 215, andthe output of the latch circuit 216 is applied to the second input B ofthe adder/subtracter circuit 218. The output of the address counter 220is applied to the input of RAM 219 and is connected to the scale codeterminal 34 through the latch circuit 221. The carry output D of theadder/subtracter 218 is connected to a control portion 217. A quantitycomparison signal from the control portion 217 is supplied to theselector 213 and OR gate 209. The latch circuit is added to latchcircuits 215, 216 and 221, a count clock is supplied to the addresscounter 220, and a read/write signal is applied to RAM 219. The data bitof the shift register 26 is applied to an enable terminal of a counter222. A clock φx is supplied to the count input of the counter 222 and aframe clock φf is applied to the reset input thereof. The multipliercircuit 28 receives the last shift output of the shift register 26 andshift data selected by the selector 27. As described above, themultiplier circuit 28 comprises the exclusive logic OR gate 28-1 and ANDgate 28-2, which receive a sign bit and data bit, respectively. A logicof the exclusive logic OR gate 28-1 coincides with a logic of a sign ofa multiplication having a positive and negative bit. A logic of the ANDgate 28-2 coincides with a logic of a multiplication of one bit data ofno sign bit. Thus the multiplication of three-valued data is conductedby the exclusive logic OR gate 28-1 and AND gate 28-1. The result isstored in latch circuits 208 and 210. The latch circuit stores amultiplied result so that the multiplied result is not changed duringthe following window processing and it stores constant data until thenext multiplied data is inputted thereto.

The ROM 212 stores window values therein. The window value correspondingto the correlative value multiplied by means of the multiplicationcircuit 28 is selected by the control portion 217, and is delivered fromthe ROM 212. In general, a correlative value obtained in relation to atime delay concerns the power of a frequency corresponding to a periodequal to the delay time. Therefore, in case of a signal containinghigher harmonics in large quantities, the correlative values of thehigher harmonics become equivalent to or greater than the value of thefundamental wave. Since the correlative values are obtained for aplurality of delay times in the present invention, the higher harmonicwave might be mistaken for the fundamental wave in such case. To the endof preventing this drawback, the correlative value is multiplied by thewindow value. The window value is greater as the delay time is longer(the frequency is lower), by way of example. Now, the window valueprovided from the ROM 212 enters the corresponding gate circuit 211,which is turned "on" or "off" by the output data of the AND gate 28-2.More specifically, if the output of the AND gate 28-2 is the high level,the window value is applied to the first input of the selector 213 inorder to add or subtract the value, and if the output is the low level,zero data is applied to the first input. At this time, the controlterminal of the selector 213 and the OR gate 209 are supplied with thelow level from the control portion 217. Thus, the selector 213 appliesthe output of the gate circuit 211 or the window value to the firstinput A of the adder/subtracter circuit 218. In addition, the OR gate209 applies the sign data of the multiplication circuit 28 to theaddition/subtracter control terminal S of the adder/subtracter circuit218. Under this status under which the selector 213 selects the outputof the gate circuit 211 and the addition/subtraction control terminal Sof the adder/subtracter circuit 218 is supplied with the sign data, thewindow value and the value entering the input B of the adder/subtractercircuit 218 are added by this circuit 218 when the three-valued data is+1, and the window value is subtracted from the valve similarly enteringthe input B when the three-valued data is -1. On the other hand, whenthe data bit is zero, that is, when the three-valued data is zero, zerois delivered from the corresponding gate circuit 213, so that the outputC of the adder/subtracter circuit 218 becomes the value having enteredthe input B. That is, the three-valued data (being the multipliedresult) and the window value are multiplied, and then added in theadder/subtracter circuit 218 by such operation. At this time, the dataof the RAM 219 assigned by the address counter 220 is applied to theinput B of the adder/subtracter circuit 218 through the latch circuit216. Since the data is the corresponding cumulative data inputted up tothat point, of the results of multiplications of the multiplicationcircuit 28 between the three-valued data and the window values, theoutput of the adder/subtracter circuit 218 becomes a cumulated resultwith the new product added. The result is stored in the latch circuit214, and is also stored in the memory area of that address of the RAM219 which is assigned by the address counter 220, and which is the sameas the address before the addition of the new product or multipliedresult.

The data bit of the output of the shift register 26 is applied to theenable terminal of the counter 222, and the clock φ_(x) is applied tothe count input thereof each time the data is shifted. Therefore, whenthe data is +1 or -1, the counter 222 counts up. On the other hand, thecounter 222 is cleared by the frame clock φ_(f). Accordingly, thecontent of the counter 222 is equivalent to the power of the three-valuequantization data during 1 frame. The output R₀ of the counter 222 isused as data for generating a flag indicative of the presence or absenceof a sound to be described later.

Further, the above operation will be explained with reference to a datachart within 1 frame shown in FIG. 6. The correlative values in theembodiment of the present invention are found in frame unit. One frameconsists of 800 data, X₀ -X₇₉₉ in all, and the correlative values arecomputed in the preceding part X₀ -X₃₉₉ (period T₁) of the frame. Beforethe period T₁ or in a period T₅ of the preceding frame, the contents ofthe RAM 219 are cleared by a circuit not shown. In addition, the dataitems x(0+τ₀)-x(0+τ₃₇) of the specified delay times at the data X₀ aresuccessively multiplied by means of the multiplication circuit 28.Further, the respective window values corresponding to themultiplications, in other words, corresponding to the delay times, aredelivered from the ROM 212 in succession. At this time, the contents ofthe RAM 219 corresponding to the delay times are successively selectedby the address counter 220. The two kinds of data are calculated in theadder/subtracter circuit 218 by the operation described before, and thecalculated results are finally stored in the RAM 219. The addresscounter 220 has count contents 0-37 corresponding to τ₀ -τ₃₇, of whichthe circuit is made at the data X₀ and further each of the data X₁-X₃₉₉. That is, the address counter 220 repeats the counting of 0-37four hundred times within 1 frame. Thus, the delay data x(j+τ₀)-x(j+τ₃₇)of the respective data X₀ -X₃₉₉ are multiplied, and the results arefurther multiplied by the window values and then cumulated.Consequently, the cumulated results corresponding to the specified delaytimes τ₀ -τ₃₇, in other words, the correlative values R'(τ_(i))indicated in the foregoing equation (2), namely, the correlative valuessubjected to the window processing, are stored as the contents of therespective addresses of the RAM 219.

In the operation mentioned above, the control portion 217 accesses theaddresses of the ROM 212 storing the window values. Since, however, theaddress correspond to the counts of the address counter 220, a similaroperation is effected by applying the counts to the ROM 212. Further,such operations as the storing operations of the latch circuits 215, 216and the RAM 219 are controlled in synchronism with clock pulse trains φ₁and φ₂ shown in FIG. 6.

The circuit arrangement of FIG. 9 further has the function of findingthe maximum value of the correlative values corresponding to therespective delay times. Now, the operation will be described.

First, the latch circuits 215 and 216 are cleared in a period T₂. Sincethe correlative values corresponding to the respective delay timesobtained in the period T₁ shown in FIG. 6 have been stored in the RAM219, the correlative value corresponding to τ₀ is addressed by theaddress counter 220 and is stored in the latch circuit 216.

Since, on this occasion, the selection terminal of the selector 213 issupplied with the high level of the selection signal, the selector 213selects the output of the latch circuit 215. Further, since one input ofthe OR gate 209 is supplied with the high level of the selection signal,the output thereof becomes the high level. That is, theaddition/subtraction control terminal S of the adder/subtracter 218 issupplied with the high level, so that the adder/subtracter circuitexecutes the subtraction operation.

As stated above, the latch circuit 216 first stores the datacorresponding to τ₀. Therefore, the adder/subtracter circuit 218subtracts the value from data stored in the latch circuit 215. At thistime, the latch circuit 215 is immediately after having been reset.Therefore, zero is stored, and a carry is provided from the carryterminal D. Upon receiving the carry signal, the control portion 217makes control so that the content of the address of the RAM 219 assignedby the address counter 220, namely, the correlative value correspondingto τ₀ at this time may be stored in the latch circuit 215. Since zerohas been stored in the latch circuit 215 at the initial stage, thecorrelative value corresponding to τ₀ is stored in the latch circuit 215without fail. On this occasion, the count value of the address counter220 is also stored in the latch circuit 221. The address counter 220 issubsequently incremented by the next clock pulse of, e.g., the train φ₁,so as to access the next address of the RAM 219 in which the correlativevalue of τ.sub. 1 is stored. Thus, the RAM 219 provides the correlativevalue of τ₁, and the latch circuit 216 stores this data in accordancewith the clock produced from the control portion 217. Similar to theforegoing, the content of the latch circuit 216 is subtracted from thatof the latch circuit 215 by the adder/subtracter circuit 218. Herein, ina case where the result is minus, that is, where the carry terminal D ofthe circuit 218 has delivered the carry, the content of the latchcircuit 216 is greater than that of the latch circuit 215. Therefore,the content of the latch circuit 216 or the data provided from the RAM219 is stored in the latch circuit 215, and the value of the addresscounter 220 is then stored in the latch circuit 221. These storingoperations are executed in accordance with the latch signal producedfrom the control portion 217. Conversely, in a case where the content ofthe latch circuit 216 is smaller than that of the latch circuit 215, nocarry is delivered form the carry terminal D. Therefore, the latchsignal is not provided from the control portion 217, and the content ofthe latch circuit 215 undergoes no change. Although the result of theadder/subtracter circuit 218 is provided, the data merely enters thelatch circuit 214 and is not delivered therefrom. Since such operationsare successively executed for τ₀ -τ₃₇, the maximum value of thecorrelative values corresponding to the delay times is finally stored inthe latch circuit 215. In this way, the maximum value of the contents ofthe RAM 219 is detected. Concurrently, the latch signal pulses enteringthe latch circuit 215 are also applied to the latch circuit 221 in thesuccessive operations for τ₀ -τ₃₇. Finally, the address of the RAM 219corresponding to the maximum value stored in the latch circuit 221 islatched in the latch circuit 221. Since the address value corresponds tothe correlative value having the maximum value, it is delivered from themusical scale code terminal 34 as the code data of the maximumcorrelative value. The delivery of the code data is done in a period T₄.

The window processing and cumulation, and the detection of the maximumvalue of the cumulated results are executed in frame units in successivefashion. In consequence, the result of the pitch extraction in the voiceduring 1 frame time, namely, during the periods T₁ -T₅ is coded anddelivered as the output. This output is the output of the pitchextraction unit 3, and it is stored in the latch 4 of the succeedingstage and is subjected to the next processing.

FIG. 10 shows a detailed circuit diagram of the error elimination unitof FIG. 1.

The error elimination circuit is described below in detail.

The output of the memory unit 6 is applied to a latch circuit 224, gate225, a B input of a comparator 226, and an A in put of a comparator 227.The output of the latch circuit 224 is connected to an adder/subtractercircuit 228 and a gate circuit 229. The output of the adder/subtractercircuit 228 is applied to an A input of a comparator 226 and a B inputof a comparator 227, through latch circuits 230 and 231, respectively.The comparison outputs of the comparators 226 and 227 are applied to anOR gate 232. The output of the OR gate 232 is applied to the first inputof an AND gate 233. The output of the AND gate is applied to a latchcircuit 234. The output of the latch circuit 234 is applied to a latch235 and gate 229, and is also applied to the gate circuit 224. Theoutput of the latch circuit 235 is applied to the second input of an ANDgate 233 through an inverter 237. The constant data C produced by aprocessor 5 (FIG. 1) is applied to one of the inputs of anadder/subtracter circuit 228. Furthermore, the control signal SUB isapplied to the first gate of an AND gate 240 through theadder/subtracter circuit 228, the first input of the AND gate 238, andan inverter 239. Clocks φ_(L2) and φ_(L1) are applied, respectively, tothe second inputs of the AND gates 238 and 240. The output thereof isapplied to the latch circuits 231 and 230. The outputs of the gatecircuits 229 and 225 are commonly connected and are applied to a circuitin the next stage, namely, the running average arithmetic unit 8 (FIG.1). On the other hand, clocks φ_(IN), φ_(L3) and φ_(L4) are applied tothe latch circuits 223, 234 and 235. A clock φ_(L4) is supplied to thelatch circuit 224.

The concrete operation of the error elimination unit 7 constructed asdescribed above, is described by referring to a timing chart of FIG. 11.

Assume that the frame of the operation be the (n-1)-th frame. At first,the pitch data P_(n-1) of the (n-1)-th frame from the memory unit 6(FIG. 1) is stored in the latch circuit 223 in accordance with the riseof the clock φ_(IN), and it is delivered to the B input of thecomparator circuit 226 and the A input of the comparator circuit 227 inaccordance with the fall of the clock φ_(IN). On the other hand, the Ainput of the comparator circuit 226 and the B input of the comparatorcircuit 227 have already been respectively supplied with values P_(n-2)+C and P_(n-2) -C obtained by adding and subtracting a constant C to andfrom the pitch data P_(n-2) of the immediately preceding frame, namely,the (n-2)-th frame. The comparator circuit 226 compares if P_(n-2)+C<P_(n-1) holds, while the comparator circuit 227 compares if P_(n-2)-C>P_(n-1) holds. When the conditions are met, the comparator circuits226 and 227 provide outputs of the low level. When either conditionholds, that is, when P_(n-1) lies outside the range of P_(n-2) ±C, oneof the comparator circuits 226 and 227 provides the output of the highlevel. As a result, the output of the OR gate 232 becomes the highlevel. Then, a high level signal is delivered through the AND gate 233.In the initial status, the latch circuit 235 is reset, and hence, itsoutput is at the low level. Therefore, the inverter 237 is supplied withthe low level, and its output becomes the high level. That is, thesecond input of the AND gate 233 is supplied with the high level.Accordingly, the AND gate 233 turns "on" to apply the output of the ORgate 232 to the latch circuit 234. If P_(n-1) lies within the range ofP_(n-2) ±C, the output of the AND gate 233 becomes the low level.Subsequently, the signal of the AND gate 233 is fed to the latch circuit234 in accordance with the rise of the closk φ_(L3), and the output ofthe latch circuit 234 appears in accordance with the fall of the clockφ_(L3).

Here, if P_(n-1) lies within the range of P_(n-2) ±C, the output of thelatch circuit 234 becomes the low level to disable the gate circuit 229.In addition, since the inverter 236 is supplied with the low level, itsoutput becomes the high level and enables the gate circuit 225. Theinput pitch data of the (n-1)-th frame as it is, is fed to the latchcircuit 241 through the gate circuit 225 in accordance with the rise ofthe next clock φ_(OUT), and it is delivered to the circuit of thesucceeding stage, namely, the running average calculation unit 8 inaccordance with the fall of the clock φ_(OUT). This occasion is a casewhere the pitch data P_(n-1) of the (n-1)-th frame lies within aspecified range (±C) relative to the immediately preceding pitch dataP_(n-2) and where it has been judged correct pitch data.

Next, if P_(n-1) lies outside the range of P_(n-2) ±C, the output of thelatch circuit 234 becomes the high level to disable the gate circuit 225and to enable the gate circuit 229. The pitch data P_(n-2) of theimmediately preceding frame having been delivered from the latch circuit224 in advance, is fed to the latch circuit 241 through the gate circuit229 in accordance with the rise of the clock φ_(OUT), and is deliveredto the circuit of the succeeding stage or the running averagecalculation unit 8 in accordance with the fall of the clock φ_(OUT).This is a case where the pitch data P_(n-1) of the (n-1)-th framediffers greatly from the immediately preceding pitch data P_(n-2).Herein, P_(n-1) is neglected as abnormal pitch data, and the pitch dataP_(n-2) of the immediately preceding frame is delivered instead.

Subsequently, the output from the latch circuit 234 is fed to the latchcircuit 235 in accordance with the rise of the clock φ_(L4), and theoutput of the latch circuit 235 is applied to the input of the AND gate233 through the inverter 237 in accordance with the fall thereof. Thelatch circuit 235 serves to store if the pitch data P_(n-1) of the(n-1)-th frame has been the normal value, and the low level of thecontent of this latch circuit indicates the normality and the high levelthe abnormality. Besides, the output P_(n-1) from the latch circuit 223enters the latch circuit 224 in accordance with the rise of the sameclock φ_(L4), and the output of the latch circuit 224 enters theadder/subtracter circuit 228 in accordance with the fall thereof. Sincethe other input of the adder/subtracter circuit 228 is supplied with theconstant value C, the addition is first conducted (the control signalSUB is at the low level).

Next, the result of the addition P_(n-1) +C enters the latch circuit 230in accordance with the rise of the clock φ_(L1), and the output of thislatch circuit 230 appears in accordance with the fall thereof.

Subsequently, the control signal SUB of the adder/subtracter circuit 228becomes the high level, and the constant value C is subtracted from theoutput P_(n-1) of the latch circuit 224. The result of the subtractionP_(n-1) -C enters the latch circuit 231 in accordance with the rise ofthe clock φ_(L2), and the output of this latch circuit 231 appears inaccordance with the fall thereof.

Then, the operations for 1 frame end, and the control shifts to the n-thframe. In the n-th frame, the pitch data P_(n) of this frame is receivedin accordance with the clock φIN. It is compared in magnitude with thevalue P_(n-1) ±C previously computed in the (n-1)-th frame. The pitchdata P_(n-1) or P_(n) based on the comparison is selectively delivered.

In the way thus far described, the pitch data which is greatly differentfrom the pitch data of the preceding frame is eliminated as the abnormaldata, and the pitch data of the preceding frame is delivered instead.

However, in a case where the musical scale changes suddenly andcontinuously, the error elimination is rather inconvenient. Therefore,in a case where the error elimination has been done in the precedingframe, it is not executed in the present-time frame. Now, when the errorelimination has been done in the preceding frame, the output of thelatch circuit 235 is the high level, so that one input to the AND gate233 to be applied through the inverter 237 becomes the low level. Thus,the output of the latch circuit 234 becomes the low level without fail,and only the gate circuit 225 is selected, with the result that theerror elimination is not executed. That is, in the event that the pitchdata items have abruptly changed for 2 or more frames, the change is notdeemed an error, and the error elimination is not done.

FIG. 12 is a diagram showing examples of the inputs of the pitch data,and examples of the outputs of the error elimination unit 7 (the outputsof the latch circuit 241) and contents of the latch circuit 235,corresponding to the input examples. The pitch data P₄ of the fourthframe has a value greater than P₃ '+C where P₃ ' denotes the outputpitch data of the third frame. Besides, the error elimination has notbeen done in the third frame (the value of the latch circuit 235 in thethird frame is "0"). Therefore, the input data P₄ is judged abnormal,and the output P₄ ' of the fourth frame is rendered the same value asthe value P₃ ' of the third frame.

Likewise, the pitch data P₈ of the eighth frame is judged abnormal, andthe output P₈ ' thereof is rendered the same value as that P₇ ' of theseventh frame. The pitch data P₉ of the ninth frame is also greater thP₈ '+C where P₈ ' denotes the output of the eighth frame. In this case,however, the error elimination has been done in the eighth frame, andthe value of the latch circuit 235 has become "1". Therefore, the inputP₉ is not judged abnormal, and it is provided as the output P₉ ' withoutbeing changed. Further, the input value P₁₀ of the tenth frame becomessmaller than P₉ '-C in relation to the output value P₉ ' of thepreceding ninth frame. Therefore, the input P₁₀ is judged abnormalagain, and the output P₁₀ ' becomes the same value as P₉ '. Thereafter,the input value P₁₁ of the eleventh frame is smaller than P₁₀ '-C inrelation to the output value P₁₀ ' of the preceding tenth frame. Since,however, the value of the latch circuit 235 is "1", the errorelimination is not done, and the data P₁₁ is delivered as P₁₁ ' withoutbeing changed. In this manner, according to the error eliminator circuitof the present invention, the error of only one frame is properlyeliminated, and in the case where the change has continued for at leasttwo frames, it is not judged and error and it can be followed up withthe response merely delayed by one frame as illustrated in FIG. 12.

FIG. 12 shows an example in which the pitch data abruptly changes from alow value to a high value. The operation is the same as described inFIG. 12. A step-shaped portion appears in the output at every two steps.The response follows fully only with one frame delay.

As described above, the error elimination portion 7 eliminates an errorof one frame caused by an error of the pitch extraction and delivers aproper musical scale to the next stage.

In the above embodiment, the pitch data is numeric number sequentiallyassigned to musical scales. The present invention is not limited to it.Pitch data may be directly corresponding to the pitch. Further, therange in which pitch data may be compared with those of the previousframe is limited to a range of a constant number C. As a change in pitchupon producing voice and an error caused in a pitch extraction portion 3are different depending on a higher frequency voice or a lower frequencyvoice, the value of the constant number C may be varied accordingly.

The data, the error of which is eliminated by the error eliminationportion, is applied to the running average calculation unit and pitchdata control unit.

FIG. 14 shows a detailed block circuit of running average calculationportion 8 of FIG. 1. The running average calculation portions will beexplained more in detail.

The output of the error elimination portion 7 is applied to a shiftregister 243 through a latch 242. The outputs of the shaft register 243and latch 244 are applied to a selector 245. The output of an octalcounter 246 to which a clock φ₀ is applied is added to the selector 246.The output of the selector 245 is applied to the first input of theadder 247. The output of the adder 247 added to the second input of theadder 247. The output of the adder 247 is added to latch circuit 249through the latch 248. The upper eight bit output of the latch circuit249 is added to the first input of an adder 250. The ninth output of thelatch circuit 289 is supplied to a carry input of an adder 250. Theoutput of the adder 250 is applied to the latch 224 through a latch 251and is outputted to a counter of the next stage, namely, the pitch datacontrol portion 10.

The pitch data, the error of which is eliminated, for example, eight bitdata, is stored in the latch circuit 242 as the data within one frame.The latch circuit 242 receives data at a running of a frame clock φ_(f)in order to process in frame units the data from which the error isdeleted.

The shift register 243 performs a shifting of 8 bit parallel data at atiming of a frame clock φ_(f). The data stored in the latch circuit 242is successively stored in the shift register 243 by every frame unitand, then, shifted. In other words, the shift register 243 memorizes sixdata previous to the present data.

On the other hand, the latch circuit 244 comprises paired latchcircuits. The latch circuit 244 receives the same data as the output ofthe running average arithmetic unit 8 and the same data is stored in thepaired latch circuits. The selector 245 sequentially selects six bytedata stored in the shift register 243 and two byte data stored in thelatch circuit 244 within one frame, thereby producing the output. Thisselection is instructed by the count value of an actual counter 246which counts up by a clock φ₀, the φ₀ comprising eight blocks within oneframe.

As the output of the adder 247 is applied to the second input thereofthrough the latch circuit 248, the output of the latch circuit 248 isconsidered as an output of a cumulating circuit for accumulating dataapplied to the first input of the adder 247 as a timing of φ₀. As thelatch circuit 248 is reset by a reset clock φ_(R) produced at the end ofone frame, the accumulation operation is conducted by every one frame.

The content of the shift register 243 and the latch circuit 244 isapplied to the first input of the adder 247 at a timing of φ₀ throughthe selector 243. Thus, the accumulated output of the aforementionedcumulating circuit is equal to the sum of the data accumulated over sixframes and twice data currently produced. Thus, the following equationis established. ##EQU3## where Dn+1˜Dn+6 are data stored in the shiftregister 243. Ds is data produced from the latch circuit 251 and Dx isthe accumulated output of the aforementioned cumulating circuit.

This adder 247 cumulates the mean value weighted and the 6 data, to findthe cumulative value for obtaining the new mean value. The data obtainedby weighting the mean value up to now is used as the data for findingthe new mean value corresponding to the next frame clock, for thefollowing reason: It is sometimes the case that proximate musicalscales, for example, "B" and "C" often arise in response to a voice "C"on account of an error of pitch extraction etc., resulting in the randomdeviations of data. The above measure is therefore adopted in order tofix the proximate data.

Since the data entering the first input of the adder 247 consists of 8bits, the aforementioned cumulative output becomes 11-bit data. It isthe succeeding latch circuit 249 and adder 250 that evaluate the outputD_(x) /8. The latch circuit 249 stores the cumulative output, the moresignificant 8 bits of which are applied to the input of the adder 250.The 9th bit is applied to the carry input of the adder 259. The 9th bitis applied to the adder 250 for the reason that the less significant 3bits of the 11 bits are not merely rounded off, but that the 9th bit istaken into account. More specifically, when the 9th bit is "1", "1" isadded to the data of the more significant 8 bits to form the averageoutput, and when the 9th bit is "0", "1" is not added, and the lesssignificant 3 bits are rounded off to provide the output. The latchcircuit 249 and adder 250 are the circuits for delivering the mean valueaccurately, as stated above, and they are not needed when a highaccuracy is not required.

The output of the adder 250 is stored in the latch circuit 251. Thislatch circuit 251 is a circuit for fixing the data during the next framebecause its output is used in the succeeding stage and cumulation duringthe frame.

To sum up, the circuit arrangement in FIG. 14 further uses the meanvalue as part of the input data, thereby producing a hysteresis effectin the averaging operation and preventing the immediate response to thechange of the less significant bits of the data.

FIG. 15 is a timing chart showing the timing clock pulse trains of therunning average calculation unit 8. Referring to this timing chart, theoperations of the circuit arrangement in FIG. 14 will be furtherexplained. The frame clock φ_(f) generates a clock at the beginning of 1frame, and stores and shifts data as required. In FIG. 14, the latchcircuits 242, 244 and the shift register 243 operate in accordance withthis clock. Upon the generation of this clock, the stored data items ofthe latches etc. are fixed for 1 frame. Next, the clock pulse φ₀ aresuccessively produced in the number of 8 during 1 frame. These clockpulses increment the octal counter 246 so as to successively select the8 input data within 1 frame by means of the selector 245. Further, theclock φ₀ serves for the cumulation. More specifically, in accordancewith the rise of the clock pulse φ₀, the octal counter 246 isincremented to select data. The selected data is applied to the adder247. At this time, the adder 247 is supplied with the addition datareceived up to this point, to which the select data is added orcumulated. In accordance with the fall of the clock pulse φ₀, the latch48 stores the resultant data. Such operations for the cumulation areexecuted 8 times during 1 frame. As described above, the cumulation isthe addition between the past 6 data and double the mean value of theprevious data. After the generation of the eighth clock pulse, a clockφ₁ is produced, and the cumulative value is stored in the latch circuit249. Almost simultaneously with the storage, the cumulative value isapplied to the adder 250. This adder adds the value and the carry statedbefore, to provide the output. This output becomes the mean value. Thisprocessing is done before a clock φ_(OUT) to be subsequently generated,and the latch circuit 251 stores and delivers the mean value N₈ (DS) inaccordance with the clock φ_(OUT). The storage of the latch circuit 248is reset by the clock φ_(R) . This clock φ_(R) serves to execute thecumulation in frame unit.

Although the foregoing circuit arrangement has obtained the new meanvalue by cumulating the 6 data and double the previous mean value, thenumber of the data is not restricted to 6, and the multiple number ofthe previous mean value is not restricted to double, either. In thiscase of rendering the number of the data or the multiple number of themean value different from that in the embodiment, a divider circuitcorresponding to the different number is necessary.

Although not explained as to the running average calculation unit 8, theaveraging of 4 frame data is also carried out. Likewise to the 8-framerunning average value N₈, the average value N₄ of the 4 frame data isapplied to the pitch data control unit 10.

FIG. 16 shows a detailed block diagram of the pitch data control portion10 of FIG. 1. The pitch data control portion 10 will be explainedhereinafter.

Regarding the human voice, even when a specified pitch is to beproduced, it is often astable at the beginning of vocalization, etc.Moreover, as stated before, the part of consonants etc. frequently leadto erroneous extractions because of unclear pitches.

On the other hand, the running average output with the hysteresis in therunning average calculation unit 8 is effective for stabilizing pitchdata on a steady musical scale, but is ineffective for a beginning partof great change. The output of the error elimination unit 7 can properlyeliminate the error of the pitch data of 1 frame and can also follow upthe sudden change of a musical scale, but it cannot follow up theunsteady change of the head part of the voice. Further, the 4-framerunning average output in the running average calculation unit 8 has aproperty intermediate between the two outputs mentioned above. Theunprocessed pitch data from the memory unit 6 is directly delivered tothe code generator 11 in e.g., the initial 1st-3rd frames after thestarting of vocalization. In the next 4th-7th frames, the pitch data isdelivered through the error elimination unit 7. In the still next8th-11th frames, the 4-frame running average output from the runningaverage calculation unit 8 is provided. In and the 12th frame, thehysteretic 8-frame running average output of the calculation unit 8 isprovided. In this way, as the beginning of the vocalization shifts tothe steady part, the pitch data properly processed is selectivelydelivered to the code generator 11.

In case of producing sounds "do-so", by way of example in the humanvocalization, when the steady part of "do" shifts to "so", a consonantexists in the initial part of "so", and hence, the pitch data sometimesinterrupted in that part. However, when musical sounds are actuallyproduced as "do-so", "do" and "so" should ideally be smoothly continuouswithout interruption. Therefore, when the consonant part has beendetected, the pitch data immediately preceding the consonant part iscontinuously delivered for the detected part and vowel parts of 1-3frames continuous thereto. In the subsequent 4-7 frames, the pitchesmight be interrupted in a consonant part to incur a great change in thepitches, and hence, the pitch data items from the respective processingportions are selectively delivered to the code generator 11 similarly tothe foregoing processing for the initial part of the vocalization.

In order to realize the above operation with the pitch data control unit10, various flags are prepared in the flag preparation unit 9 (FIG. 1).The flags to be prepared consist of a power flag PF, voice "presence" or"absence" flag CF, key-on flag KOF, key attack flag KATF and key-offflat KOFF. First, the power flag PF will be described.

Besides the pitch data, the power of the voice data of each frame (theoutput of the power extraction terminal 24 in FIG. 2) is delivered fromthe pitch extraction unit 3 to the processor 5 through the latch 4. Whenthe value of the power has exceeded a certain threshold value, the powerflag PF becomes the high level. This power flag PF serves as theindicator of the presence of a voice, regardless of whether it isconsonant or a vowel.

Further, the processor 5 is supplied with the output R₀ of the counter222 shown in FIG. 9. This output data is the cumulative value of theabsolute values of the three-value quantization data during one frame.When the output R₀ has exceeded a certain threshold value, the voice"presence" or "absence" flag CF becomes high level. The voice "presence"or "absence" flag CF indicates the degree of the presence of a pitch.This flag CF becomes high level for a vowel sound etc., but it becomes alow level for a consonant sound or no sound. Since the voice "presence"or "absence" flag CF is a barometer expressing whether or not thecorrelative value is valid, the use of the maximum correlative valuefound is also allowed.

The key-on flag KOF is the flag showing that the musical instrument isin a state of producing sound. The key-on flag KOF turns to a high-levelwhen both the power flag PF and the correlative value flag CF are in thehigh level. The key-on flag KOF turns to a low level when both the powerflag PF and the correlative value flag CF are in the low level. In othersituations than the above, it does not change. A key attack flag KATFbecomes high level only during the first one clock in which the key-onflag KOF turns to the high level. The key-off flag KOFF becomes highlevel only during the first one clock in which the key-on flag KOFbecomes low level.

These two flags are used as an index for indicating the beginning andend of the sound production. The operation of forming two flags isperformed in every frame and is synchronized with a frame clock φ_(f)having a time width of a frame interval.

It is determined by using five flags above described whether it is aframe of voice start, a frame of consonant or a frame of voice end. Theframe of voice start is a frame in which the key attack flag KATF is inthe high level, and the frame of voice end is a frame immediately priorto a timing at which the key-off flag KOFF becomes a high level. Theconsonant frame is the frame in which both the power flag PF and key-onflag KOF are in the high level and the voice "presence" or "absence"flag CF is in the low level. In order to perform the pitch data controloperation based on the above-mentioned flags, the pitch control unit 10uses a counter (ANC) 267 for counting eleven frames from the frame ofvoice start and a counter (SNC) 268 for counting the eleven frames fromthe frame following to the consonant frame.

Thus, pitch data N₁ which is not yet processed is transmitted from thememory portion 6 (FIG. 1) to a latch circuit 263 through a latch circuit254 and gate circuit 253. Pitch data N₂ is transmitted from the errorelimination portion 7 (FIG. 1) to the latch circuit 263 through a latchcircuit 255 and gate circuit 259. Average output pitch data N₄ outputtedfrom the running average arithmetic unit 8 is supplied to the latchcircuit 263 through a latch circuit 256 and gate circuit 260. Therunning average output with hystereis, namely, running average pitchdata N₈, is supplied from the running average arithmetic unit 8 to thelatch circuit 263 through a latch circuit 257 and a gate circuit 261.The output of the latch circuit 263 is delivered to the code generator11 (FIG. 1) and is fed back to its own input through a latch circuit 264and gate 262. The key-on flag KOF from the flag formation unit 9(FIG. 1) is supplied to the count enabling input EN of the counters 267and 268 through AND gates, respectively. Further more, the signal KOF isapplied to an OR gate 270 through an inverter 269. The power flag PF andvoice "presence" or "absence" flag CF from the flag formation portion 9are applied to a NAND gate 271 and the output thereof is supplied to thecount reset input R of the counters 267 and 268 and to an OR gate 270.The key-attack flag KATF from the flag formation portion 9 and therespective bit outputs delivered from the counter 267 through the ORgate 274 are applied to a count enabling input EN of the counter 267through the AND gate 265 through an OR gate 276 and AND gate 265. Thevoice "presence" or "absence" flag CF from the flag formation unit 9 issupplied to a latch circuit 277 operating in accordance with the frameclock φ_(f) and the output of the latch circuit 277 is added to a latchcircuit 278. The output of the latch circuit 277 and the output of thelatch circuit 278 through an inverter 270 are applied to an AND gate280. The output of the AND gate 280 and the respective bit outputs ofthe counter 268 through an OR gate 275 are added to the count enableinput EN of the counter 268 through an OR gate 281 and AND gate 266. Thecounters 267 and 268 perform a count in accordance with the frame clockφ_(f) and the respective bit outputs thereof are added to logic circuits282 and 283. The outputs 284 and 291 which become high level when thecount is zero, are commonly supplied to the gate 261 through an OR gate290 and one input of an AND gate 296. The other input of the AND gate296 receives an output of the OR gate 270 through an inverter 297. Theoutput 285 of the logic circuit 283 which becomes high level when thecount is one to three controls the gate circuit 258 and the output 292of the logic circuit 283 which becomes high level when the count is oneto three is added to the OR gate 270. The respective outputs 286 and 293of the logic circuits 282 and 283 which become high level when the countis four to seven control the gate circuit 259 through an OR gate 298.The respective outputs 287 and 294 of the logic circuits 282 and 283which become high level when the count is eight to eleven control thegate 260 through an OR gate 299. The respective outputs 288 and 295which become high level when the count is twelve are respectivelysupplied to the reset inputs R of the counters 267 and 268 through theOR gates 272 and 268 through the OR gates 272 and 273. The output of theOR gate 270 controls the gate circuit 262.

The operation of the pitch data control in the pitch control unit 10 asconstructed above will be explained by referring to FIG. 17.

FIG. 17 is a timing chart showing the relationships between therespective flags and the pitch data items which are delivered from thetwo counters 267 and 268 and the pitch data control unit 10 to the codegenerator 11. First, when a voice has been received, the power flag PFbecomes high level. With a delay of 2 frames, the voice "presence" or"absence" flag CF becomes high level (the delay is attributed to thecircuit arrangement). With the subsequent delay of 2 frames, the key-onflag KOF becomes high level, while at the same time the key attack flagKATF becomes high level for 1 frame. Subject to the condition that theflag KATF has become high level and that all the flags KOF, PF and CFare high level, the counter 267 starts counting. This condition is heldin such a manner that the count enable input EN of the counter 267becomes high level through the OR gate 276 and the AND gate 265. Whenthe counting has been started, the flag KATF becomes low level. Since,however, at least one of the 4 bits of the output of the counter 267becomes high level, the output of the OR gate 274 becomes high level andthe count enable input EN becomes high level through the OR gate 276 aswell as the AND gate 265, so that the counter 267 continues thecounting. Owing to the counting operation, extraction data items arecontinuously selected and delivered as outputs.

Next, when the count value of the counter 267 is 1 to 3, the gate 258 isopened, and the pitch data N₁ which is transmitted from the memory unit6 (FIG. 1) without being processed is selectively supplied to the codegenerator 11 through the latch 263. The operation can be performed whenthe output 285 of the logic circuit 282 is in high level. When the countvalue of the counter 267 is 4 to 7, the output 286 of the logic circuit282 is in high level, and the high level signal is added to the controlterminal of the gate circuit 259 through the OR circuit 298, therebycausing the gate circuit 259 open, the pitch data N₂ delivered from theerror elimination portion 7 to the latch circuit 255 is selectivelysupplied to the latch circuit 263. When the count values are 8 to 11,the gate 260 is opened, the four frame running average output N₄delivered from the running average arithmetic portion 8 and stored inthe latch circuit 256 is selectively supplied to the latch circuit 263.This operation is performed when the output 287 of the logic circuit 282is in high level thereby causing the high level signal to be supplied tothe control terminal of the gate circuit 260 through the OR gate 299.

When the count value of the counter becomes 12, the output 288 of thelogic circuit 282 becomes high level, thereby causing the counter 267 tobe elevated through the OR gate 272 and terminating the countingoperation. Then, under the condition that the power flag PF, voice"presence" or "absense" flag CF and key-on flag KOF are commonly high,the gate circuit 261 is opened, and thus, the running average outputdelivered from the running average output N₈ with hysteresis functionand stored in the latch circuit 257 is selectively delivered to thelatch circuit 263. This operation can be performed when the output 284of the logic circuit 282 and the signal transmitted through the NANDgate 271, OR gate 270 and inverter 297 are in high level, therebycausing the output of the AND gate 296 to be high level and to beapplied to the control terminal of the gate circuit 261.

Where the consonant frame is detected in a key-on state (the key-on flagKOF is high), namely, the power flag PF is in high level and the voice"presence" or "absence" flag CF is low, the gate circuit 262 is opened,and the pitch data BN of the immediately preceding frame stored in thelatch circuit 264 is selectively transmitted to the latch circuit 263.The pitch data BN is N₈ in FIG. 17. This operation can be achieved bycausing the output of the NAND circuit 271 and OR circuit 270 to be highlevel thereby applying the high level signal to the control terminal ofthe gate circuit 262. When the consonant frame terminates and the nextvoice production frame initiates, the counter 268 starts its countingoperation. When the "presence" or "absence" flag rises to a high levelduring the period of the high key-on flag KOF, the counter 268 startsthe counting operation. This operation can be achieved by supplying apulse signal to a count enable input EN of the counter 268 through thelatches 277 and 298, AND circuit 280, OR gate 281 and AND gate 281.

When the count starts, the count enable input EN becomes a high levelthrough an OR gates 275, and 281 and AND gate 266, thereby causing thecount to continue.

When the count value is 1 to 3, the pitch data BN of the consonant framecontinue to be supplied to the latch circuit 262. This operation can beachieved by causing the output 292 of the logic circuit 283 to be in thehigh level, thereby opening the gate 262 through the OR gate 270.

When the count value of the counter 268 is 4 to 7, the gate 259 isopened as in the counter 267, the pitch data N₂ is selectively suppliedto the latch circuit 263. This operation can be achieved by causing theoutput 293 of the logic circuit 283 to be in the high level, therebyopening the gate circuit 259.

Further when the count value of the counter 268 is 8 to 11, the gatecircuit 260 is opened as in the counter 267, thereby selectivelyapplying the pitch data N₄ to the latch circuit 263. This operation canbe achieved by causing the output 294 of the logic circuit 283 to be inthe high level, thereby opening the gate circuit 260. In the frame inwhich the count value exceeds 11, the output 295 of the logic circuit283 clears the counter 268, thereby causing the counting operation toend. Thereafter, the gate circuit 261 is opened, thereby causing thepitch data N₈ to be selectively applied to the latch circuit 263. Thisoperation can be achieved by causing the output 291 of the logic circuit283 to be in the high level, thereby opening the gate circuit 261.

The vocalization might continue unstably until, in the last part of thevocalization, the flag CF and then the flag PF become low level and theflag KOF becomes low level with a delay of 2 frames. Therefore, the gatecircuit 262 is enabled, and the pitch data BN of the immediatelypreceding frame (N₈ in the case of FIG. 17) is similarly delivered tothe latch circuit 263 selectively.

This operation is realized by enabling the gate circuit 262 through theNAND gate 271 as well as the OR gate 270.

FIG. 18 collectively indicates the relationships between the countvalues of the counters 267 and 268 and the sorts of pitch data to beselected. When the count values of the respective counters are 1-3, theunprocessed pitch data N₁ is selected in the counter 267 because of thestarting of the vocalization, while the pitch data BN of the framedirectly preceding a consonant is selected in the counter 268 because ofthe frame succeeding the consonant.

Further, as regards the count values 4-7 and 8-11 in the initial part ofthe vocalization, the unprocessed pitch data, the pitch data obtained byexecuting the error elimination of 1 frame, the pitch data obtained bytaking the running average of 4 frames, and the pitch data obtained bytaking the hysteretic 8-frame running average are selectively adopted inthe order mentioned. Therefore, the pitch data of slight erroneousextraction can be supplied to the code generator 11 for both theunsteady change and the steady part. Moreover, the pitch data items aresmoothly connected without interruption in the consonant part and theend part of the vocalization, so that the change of the musical scalesto be produced in the code generator 11 becomes natural. In theembodiment of the present invention, the "off" of the voice "presence"or "absence" flag CF has been set at the consonant part. However, it isnot restricted to the consonant part, but the change of musical scalesproduced from a musical instrument, for example, also correspondsthereto.

As described above, the present invention provides an electronic musicalinstrument in which the musical sound can be produced in accordance withthe voice input. The electronic musical instrument of the presentinvention can be firstly achieved by the three value quantizationcircuit in which stable three value data can be obtained by changing thethreshold level in accordance with the input level of voice, secondly bythe pitch extraction processing circuit for extracting the pitch of theinput voice on the basis of the time correlative value of three valuedata obtained by the three value quantization circuit, thirdly by theerror elimination circuit for detecting and correcting the error inextracting the pitch data of the input voice, fourthly by the movingaverage arithmetic circuit for stabilizing unstable change of the inputvoice and fifthly by the pitch data control circuit for selecting theprocessed result in accordance with the power of the input voice.

Accordingly, the present invention can provide an electronic musicalinstrument in which an error is not produced even if a level of an inputvoice is changed, by performing a digital detecting and processing ofthe input voice signal with the result that the instrument can by easilyperformed by the voice of the performer who does not have a skill inoperating the musical instrument.

It should be further noted that the electronic musical instrument of thepresent invention is suitable for LSI as the preprocess unit 2 and pitchextraction unit 3 can be formed in one chip.

What is claimed is:
 1. An electronic musical instrument comprising:a.[.microphone.]. .Iadd.conversion means .Iaddend.for converting a.[.human voice.]. .Iadd.musical sound .Iaddend.to an electrical signal;analog-to-digital conversion means for converting said electrical signalto digital data corresponding to an amplitude value of the .[.humanvoice.]. .Iadd.musical sound.Iaddend.; quantization means for quantizingsaid digital data outputted from said analog-to-digital conversionmeans, based on an amplitude value of the .[.human voice.]..Iadd.musical sound.Iaddend., and for producing a digital quantizationdata signal; and pitch extraction means coupled to said quantizationmeans for extracting pitch data of said digital quantization dataobtained by said quantization means, and for producing an outputcorresponding to the extracted pitch data, thereby obtaining said pitchdata as a function of an amplitude value of the .[.human voice.]..Iadd.musical sound.Iaddend.; processing means for processing the outputof said pitch extraction means; and musical tone production means forreceiving the output of said processing means and for producing amusical tone in accordance with said output of said processing means. 2.The electronic musical instrument according to claim 1, wherein saidpitch extraction means includes means for obtaining the pitch of saiddigital quantization data based on a time correlation between saiddigital quantization data.
 3. The electronic musical instrumentaccording to claim 1 in which said quantization means comprises maximumand minimum value detecting means for detecting at least either themaximum value or the minimum value of the output of saidanalog-to-digital conversion means and threshold level output means forreceiving the output of the maximum and minimum value detecting meansfor obtaining the threshold level therefrom; and said quantization meanscomprises means for receiving both the output of said analog-to-digitalconversion means and threshold means.
 4. The electronic musicalinstrument according to claim 3, in which said threshold level outputmeans comprises a memory to an address of which the output of saidmaximum and minimum value detecting means is supplied, therebydelivering data as a threshold level from the output thereof.
 5. Theelectronic musical instrument according to claim 3 in which saidreceiving means of said quantization means includes comparing means towhich the output of said analog-to-digital conversion means and theoutput of said threshold level output means are applied.
 6. Theelectronic musical instrument according to claim 5 in which saidcomparing means comprises a subtracting circuit for producing a carryoutput as a comparison output.
 7. An electronic musical instrumentcomprising:detection means for detecting a time position of at least aninitial part of a .[.human voice.]. .Iadd.musical .Iaddend.sound and aterminal part of said .[.human voice.]. .Iadd.musical .Iaddend.sound,extraction means for extracting pitch data of said .[.voice.]..Iadd.musical sound.Iaddend., a plurality of processing means forprocessing said such data is respective different manners, selectionmeans for successively selecting processed pitch data of said pluralprocessing means is correspondence with said detected time position, andmusical tone production means for producing a musical tone on a basis ofthe processed pitch data derived from said selection means, saiddetection means comprising extraction change detection means fordetecting that a change is output of said extraction means is more thana predetermined value, thereby obtaining said time position of at leastsaid initial part of said .[.human voice.]. .Iadd.musical .Iaddend.soundand said terminal part of said .[.human voice.]. .Iadd.musical.Iaddend.sound.
 8. The electronic musical instrument according to claim7 in which said selecting means comprises a counter for starting a countfrom a time position immediately following either the timing position ofa .[.voice.]. .Iadd.musical sound .Iaddend.start or that obtained fromsaid extraction change detection means, and means for selecting theprocessed pitch data in accordance with the count output from saidcounter.
 9. The electronic musical instrument according to claim 7 inwhich said selecting means comprises means for continuously deliveringthat portion of the processed pitch data which immediately precedes atime position immediately following a .[.voice.]. .Iadd.musical sound.Iaddend.end or that obtained from said extraction change detectionmeans.
 10. The electronic musical instrument according to claim 7 inwhich said plural processing means comprise means for eliminating anerror from the extracted data and means for obtaining an average of saidextracted data.
 11. An electronic musical instrument comprising:a.[.microphone.]. .Iadd.conversion means .Iaddend.for converting a.[.human voice.]. .Iadd.musical sound .Iaddend.to an electrical signal;analog-to-digital .[.conversion.]. .Iadd.converter .Iaddend.meanscoupled to said .[.microphone.]. .Iadd.conversion means .Iaddend.forconverting said electrical signal to digital data; quantization meansfor quantizing the output of said analog-to-digital .[.conversion.]..Iadd.converter .Iaddend.means and for producing a digital quantizationdata signal, pitch extraction means coupled to said quantization meansfor extracting a pitch of said digital quantization data obtained bysaid quantization means, and for producing an output corresponding tothe extracted pitch; said pitch extraction means comprising:a memory fordelaying .[.voice.]. .Iadd.musical sound .Iaddend.data.[.:.]..Iadd.;.Iaddend. a multiplication circuit for multiplying the delayed.[.voiced.]. .Iadd.musical sound .Iaddend.data from said memory by datacorresponding to a musical scale; and an output control circuit forselectively applying first data stored in said memory and second datadelayed by a predetermined time from said first data to saidmultiplication circuit; processing means for producing the output ofsaid pitch extraction means; and musical tone production means forreceiving the output of said processing means and for producing amusical tone in accordance with said output of said processing means.12. The electronic musical instrument according to claim 11 in whichsaid pitch extraction means further comprises an accumulating circuitfor accumulating and storing the output of said multiplying circuit. 13.The electronic musical instrument according to claim 11 in which saidquantization data comprises two bit data having a sign bit and a databit, and said multiplying circuit comprises an exclusive logic OR gateand AND gate, said sign bit being applied to the exclusive logic OR gateand said data bit being added to said AND gate.
 14. An electronicmusical instrument comprising:a .[.microphone.]. .Iadd.conversion means.Iaddend.for converting a .[.human voice.]. .Iadd.musical sound.Iaddend.to an electrical signal; analog-to-digital .[.conversion.]..Iadd.converter .Iaddend.means coupled to said .[.microphone.]..Iadd.conversion means .Iaddend.for converting said electrical signal todigital data; quantization means for quantizing the output of saidanalog-to-digital .[.conversion.]. .Iadd.converter .Iaddend.means andfor producing a digital quantization data signal; pitch extraction meanscoupled to said quantization means for extracting a pitch of saiddigital quantization data obtained by said quantization means, and forproducing an output corresponding to the extracted pitch; processingmeans for processing the output of said pitch extraction means; andmusical tone production means for receiving the output of saidprocessing means and for producing a musical tone in accordance withsaid output of said processing means; said pitch extraction means havinga three value correlation function processing apparatus comprising amultiplication circuit for multiplying three value data, a window valuegenerator for producing a window value, a gate circuit having a controlterminal for receiving a data bit of said multiplication circuit and aninput terminal for receiving the window value of said window valuegenerator, an adder/subtracter circuit having an adder/subtractercontrol terminal for receiving the sign bit of said multiplicationcircuit and a first input for receiving the output of said gate circuit,and a memory circuit for storing an arithmetic output of saidadder/subtracter circuit to deliver it to a second input of theadder/subtracter circuit.
 15. The electronic musical instrumentaccording to claim 14 in which said window value generating circuitcomprises a memory for storing the window value.
 16. The electronicmusical instrument according to claim 14 in which said multiplicationcircuit means comprises an exclusive logic OR gate and AND gate, anoutput of said exclusive logic OR gate operating as a sign bit and anoutput of said AND gate operating as a data bit.
 17. The electronicmusical instrument according to claim 14 in which said three valuecorrelation function processing apparatus further comprises an addresscounter for delivering its output to an address terminal of said memorycircuit.
 18. An electronic musical instrument comprising:a.[.microphone.]. .Iadd.conversion means .Iaddend.for converting a.[.human voice.]. .Iadd.musical sound .Iaddend.to an electrical signal;analog-to-digital .[.conversion.]. .Iadd.converter .Iaddend.meanscoupled to said .[.microphone.]. .Iadd.conversion means .Iaddend.forconverting said electrical signal to digital data; quantization meansfor quantizing the output of said analog-to-digital .[.conversion.]..Iadd.converter .Iaddend.means and for producing a digital quantizationdata signal; pitch extraction means coupled to said quantization meansfor extracting a pitch of said digital quantization data obtained bysaid quantization means, and for producing an output corresponding tothe extracted pitch; processing means for processing the output of saidpitch extraction means, said processing means including:an erroreliminating means comprising memory means for storing past input data;means for comparing said past input data stored in said memory meanswith present input data; and selecting means for selectively deliveringsaid past input data or said present input data, said comparison meansdetermining whether said present input data is within a predeterminedrange with regard to said past input data and selectively deliveringeither said past input data or said present input data; and musical toneproduction means for receiving the output of said processing means andfor producing a musical tone in accordance with said output of saidprocessing means.
 19. The electronic musical instrument according toclaim 18 in which said comparing means comprises an adder/subtractercircuit and a comparator, said adder/subtracter circuit addingpredetermined value to, or subtracting the predetermined value from, thepast input data, and said comparator comparing said added result andsubtracted result with the present input data.
 20. The electronicmusical instrument according to claim 18 in which said selecting meanscomprises a memory .Iadd.said .Iaddend.selecting means selecting eitherone of the past input data and the present input data based on thecontent of said memory circuit.
 21. An electronic musical instrumentcomprising:a .[.microphone.]. .Iadd.conversion means .Iaddend.forconverting a .[.human voice.]. .Iadd.musical sound .Iaddend.to anelectrical signal; analog-to-digital .[.conversion.]. .Iadd.converter.Iaddend.means coupled to said .[.microphone.]. .Iadd.conversion means.Iaddend.for converting said electrical signal to digital data;quantization means for quantizing the output of said analog-to-digital.[.conversion.]. .Iadd.converter .Iaddend.means and for producing adigital quantization data signal; and pitch extraction means coupled tosaid quantization means for extracting a pitch of said digitalquantization data obtained by said quantization means, and for producingan output corresponding to the extracted pitch; processing means forprocessing the output of said pitch extraction means; said processingmeans including:a running average arithmetic means comprising memorymeans for storing the input data; accumulation means for selecting dataof said memory means and for accumulating said selected data; andaverage means for obtaining the average of the result of theaccumulation by said accumulation means and selecting the output of saidmemory means and the output of said average means to accumulate them,thereby obtaining the average thereof; and musical tone production meansfor receiving the output of said processing means and for producing amusical tone in accordance with said output of said processing means.22. The electronic musical instrument according to claim 21 in whichsaid memory means comprises a shift register.
 23. The electronic musicalinstrument according to claim 21 in which said accumulation meanscomprises a counter, selector and adder, said selector selecting theoutputs of said memory and said output means in accordance with thecontent of said counter, and applying the selected data to a first inputof said adder and supplying the output of said adder to a second inputof said adder.
 24. The electronic musical instrument according to claim21 in which said average means includes a half adder, more significantplural bits of said accumulation means being added to the input of saidadder and one bit following the more significant six bits being added toa carry input of said adder. .Iadd.
 25. An electronic musical instrumentcomprising:conversion means for converting a musical sound to anelectrical signal; analog-to-digital converter means for converting saidelectrical signal to digital data corresponding to an amplitude value ofthe musical sound; quantization means for quantizing said digital dataoutputted from said analog-to-digital converter means, based on anamplitude value of the musical sound, and for producing a digitalquantization data signal; pitch extraction means coupled to saidquantization means for extracting pitch data from said digitalquantization data signal, and for producing an output corresponding tothe extracted pitch data; and designating means coupled to said pitchextraction means for designating the pitch of a musical tone to beobtained based on the extracted pitch data. .Iaddend. .Iadd.
 26. Anelectronic musical instrument comprising:conversion means for convertinga musical sound having a pitch to a corresponding electrical signal;analog-to-digital converter means coupled to said conversion means forconverting said electrical signal to digital data; quantization meansfor quantizing the output of said analog-to-digital converter means andfor producing a digital quantization data signal; pitch extraction meanscoupled to said quantization means for extracting pitch data from saiddigital quantization data signal, and for producing an outputcorresponding to the extracted pitch data; processing means forproducing the output of said pitch extraction means, said processingmeans including:(a) an error eliminating means comprising memory meansfor storing past extracted pitch data, (b) means for comparing saidfirst extracted pitch data with present extracted pitch data, and (c)selecting means for selectively delivering said past extracted pitchdata or said present extracted pitch data in accordance with a result ofsaid comparison, said comparing means determining whether said presentextracted pitch data is within a predetermined range with regard to saidpast extracted pitch data; and designating means for designating thepitch of a sound to be obtained based on the pitch data derived from theprocessing means. .Iaddend. .Iadd.27. An electronic musical instrumentcomprising: conversion means for converting musical sound having a pitchto a corresponding electrical signal; analog-to-digital converter meanscoupled to said conversion means for converting said electrical signalto a digital signal; quantization means for quantizing the output ofsaid analog-to-digital converter means and for producing a digital datasignal; pitch extraction means coupled to said quantization means forextracting a pitch signal from said digital signal, and for producing anoutput corresponding to the extracted pitch signal; processing means forprocessing the output of said pitch extraction means, said processingmeans including an averaging means for determining the average of aplurality of pitch signals output by said pitch extraction means toobtain an averaged pitch signal; and designating means for designatingthe pitch of a sound to be obtained based on the averaged pitch signal..Iaddend. .Iadd.28. An electronic musical instrumentcomprising:conversion means for converting a musical sound having apitch to a corresponding electrical signal; analog-to-digital convertermeans coupled to said conversion means for converting said electricalsignal to a digital signal; quantization means for quantizing the outputof said analog-to-digital converter means and for producing a digitaldata signal; pitch extraction means coupled to said quantization meansfor extracting a pitch signal from said digital signal, and forproducing an output corresponding to the extracted pitch signal; powerdetecting means coupled to said analog-to-digital converter means fordetecting power of the digital signal to generate a power signal whichis proportional to the energy of the input signal; and designating meansfor designating the pitch and the characteristic of a sound to begenerated in accordance with the extracted pitch signal and the powersignal. .Iaddend.